1. Field of the Invention
The present invention relates to a pattern layout of a semiconductor memory device. More particularly, the present invention relates to a pattern layout of word line driving gate circuits.
2. Description of the Related Art
Large computers and supercomputers offer increasingly sophisticated computation functions. Along with the increase in functions computers have become increasingly large in size. This has led to demands for miniaturization of computers.
Large-scale computers and supercomputers must operate at a very high speed in order to perform massive computations in a short time period. Bipolar circuits are used for the logic circuits. Bipolar memories, which can carry out read and write operations at a very high speed, are mainly used for the memory circuits.
A tremendously large number of bipolar memories are used in a computer. Therefore, to cope with demands for miniaturization of computers, it is required that bipolar memories be developed which are more highly integrated and smaller in size.
A bipolar memory is mainly composed of a memory cell having a flip-flop construction, an X-decoder, a Y-decoder, word line driver circuits, write/read circuits, and the like. In the prior art, the word line driving gate circuits for driving the word lines have usually been arranged at the ends of the word lines. This is because the patterns of prior art memory cells have been nearly equal in size to one of the transistors forming the word line driving gate circuits. Arrangement in a line of transistors forming the word line driving gate circuits within a block enables the width of the patterns of the driver circuits to be made approximately equal to that of the memory cells. This has been a very rational and appropriate pattern layout.
In such bipolar memories, however, the memory cells have been made increasingly denser and integrated due to the miniaturization of the transistors forming the same. On the other hand, the word line driving gate circuits have to use transistors having a large current capacity just as in the past. This is because:
(1) Cells in a bipolar memory are driven by current flowing from the word lines to the cells; PA0 (2) It is desirable to drive cells with a large current to speed up the operation of the cells; and PA0 (3) Even if cells are miniaturized and the driving current per cell decreased, the number of cells connected to a word line would be increased so as to attain the highest integration possible, resulting in the same driving current per word line. As a result, the pattern dimensions of the word line driving gate circuit cannot be reduced.
Accordingly, in the prior art pattern layout, the word line driving gate circuits obstruct attempts to achieve a higher density and greater integrated memory through miniaturization of memory cells. This results in wasted space between word lines. Moreover, it is desirable to make effective use of the space produced by wide power supply conductors.